1. Field of the Invention
This invention relates to power-on/off reset circuits that reset semiconductor integrated circuits in power-on mode and power-off mode.
2. Description of the Related Art
FIG. 7A shows a typical example of a reset circuit that operates in a power-on mode. This reset circuit comprises a capacitor CL, a p-type field effect transistor (FET) MP1, and an inverter I1. Specifically, one end of the capacitor CL is grounded, while the other end (corresponding to a terminal POC) is connected with a positive source voltage VDD via the p-type FET MP1 and is also connected with an input of the inverter I1. At time t0, the positive source voltage VDD starts increasing the level thereof as shown in FIG. 7B, so that the capacitor CL starts being charged. During the progression of the charging of the capacitor CL, the potential of the terminal POC gradually increases. Since the input voltage of the inverter I1 connected with the terminal POC is normally below the prescribed threshold allowing inversion of the inverter I1, the output of the inverter I1 (see xe2x80x98OUTxe2x80x99 shown in FIG. 7C) gradually increases in accordance with the increase of the source voltage VDD. At time t1 when a certain time has elapsed after the source voltage VDD reaches the prescribed level, the potential of the terminal POC exceeds the threshold so as to allow an inversion of the inverter I1. Therefore, in the rise time of the source voltage VDD, the reset circuit of FIG. 7A provides at the output (OUT) thereof a reset signal having a high (H) level, which is designated by a symbol xe2x80x98Rxe2x80x99 in FIG. 7C. However, the aforementioned reset circuit has a drawback in that it cannot output a reset signal in a power-off mode. This will be described further with reference to FIGS. 10A to 10C. In the reset circuit shown in FIG. 10A which is an equivalent of the reset circuit of FIG. 7A, the source voltage VDD gradually drops in a power-off mode as shown in FIG. 10B, while the potential of the terminal POC correspondingly drops with a certain delay time due to the time constant of the capacitor CL and the FET MP1. For this reason, the input voltage of the inverter I1 connected with the terminal POC would not be reduced to be lower than the source voltage VDD, so that the output of the inverter I1 remains at a low level (LO) as shown in FIG. 10C. That is, the aforementioned reset circuit of FIG. 10A cannot reliably provide a reset signal in a power-off mode.
It is strongly demanded in semiconductor integrated circuits (ICs) and LSI devices that reset signals are reliably provided in a power-off mode, which will be described below.
Suppose that two integrated circuits IC1 and IC2 operate independently of each other by their respective power sources as shown in FIG. 8, wherein the integrated circuit IC1 provides control signals to control the operation of the integrated circuit IC2. If the integrated circuit IC1 does not provide a reset function in a power-off mode, it may provide xe2x80x98unexpectedxe2x80x99 control signals to the integrated circuit IC2, which may cause problems unexpectedly. In the worst case, the integrated circuit IC2 may run away and depart from the normal operation. Therefore, it is required that the integrated circuit IC1 reliably provides a reset function in a power-off mode, which will ensure that the integrated circuit IC2 will be normally set without problems.
Suppose that an integrated circuit (IC) has a function of ringing sound by a speaker as shown in FIG. 9. If it does not provide a reset function in a power-off mode, the speaker may unexpectedly produce a high-pitch electronic sound like xe2x80x98peepxe2x80x99, which is offensive.
It is an object of the invention to provide a power on/off reset that is capable of reliably providing reset signals in both a power-on mode and a power-off mode.
A power-on/off reset circuit comprises a capacitor, a first transistor, a second transistor, a first current mirror circuit, a second current mirror circuit, and an inverter. In a power-on mode where the source voltage (VDD) gradually increases in level, the capacitor is charged via the first transistor. The first current mirror circuit comprising a pair of transistors allows a current to flow therein in proportion to a potential of the capacitor. The second transistor converts the current to a voltage, which is input to the inverter to provide a first reset signal in the power-on mode. In a power-off mode where the source voltage gradually decreases in level, the second current mirror circuit comprising a pair of transistors temporarily increases the input voltage of the inverter to provide a second reset signal.
Thus, the power-on/off reset circuit is capable of reliably providing reset signals in both the power-on mode and power-off mode.